1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an output circuit of CMOS (complementary insulated gate type) structure having a latch circuit for temporarily latching an input signal until fluctuations in the power source voltage caused at the time of a change of an output signal are suppressed.
2. Description of the Related Art
Fluctuations in potentials of the power source and ground lines of an integrated circuit are caused when outputs of the integrated circuit are changed. The influence upon the threshold voltage of an input circuit by such fluctuations becomes larger as an operation speed of the integrated circuit is increased and the driving capability thereof is also increased. More particularly, since the operation speed of the integrated circuit is increased, an abrupt variation in the voltage across the inductances of the power source and ground lines may occur when an abrupt variation in the output current occurs at the times of rise and fall of the output signal. As a result, the potential fluctuation between the power source and ground lines (referred to as "power source fluctuation" hereinafter) may cause an erroneous operation or an oscillation in the integrated circuit.
As a countermeasure for the above drawback, it has been proposed to use a Schmitt circuit in which a hysteresis voltage width is set to include when the influence upon the input signal owing to the power source fluctuation may be, expected. As another countermeasure, a technique of latching an input signal until the power source fluctuation is suppressed has also been proposed, like circuits shown in FIGS. 1 and 3 (Japanese Patent Disclosure No. 63-132523 "INTEGRATED CIRCUIT").
FIG. 1 is a circuit diagram showing an arrangement of the conventional output circuit using a latch circuit. In FIG. 1, reference numeral 14 denotes a first inverter circuit for inverting an input signal; 16, a second inverter circuit for inverting an output signal of the first inverter circuit 14; 18, a third inverter circuit for inverting an output signal of the second inverter circuit 16; 20, an output buffer circuit for buffer-amplifying an output signal of the third inverter circuit 18 and outputting the same to an output terminal 22; 24, an equivalent capacitor on the output terminal side; and 27, a feedback control delay circuit for delaying an output signal of the output buffer circuit 20 by a predetermined period of time. The delay circuit 27 is constructed by three series-connected inverters 28, 30 and 32. Each of the above circuits is supplied with a power source potential (V.sub.cc potential) and a ground potential (V.sub.ss potential) as operation power source voltages.
Further, reference numeral 40 denotes a P-channel transistor connected between the V.sub.cc potential and the output terminal of the first inverter circuit 14; 38, a P-channel transistor connected between the V.sub.cc potential and the gate of the P-channel transistor 40; 34, a third P-channel transistor connected between the gate of the P-channel transistor 40 and the output terminal of the second inverter circuit 16; 44, an N-channel transistor connected between the output terminal of the first inverter circuit 14 and the V.sub.ss potential; 42, an N-channel transistor connected between the gate of the N-channel transistor 44 and the V.sub.ss potential; and 36, an N-channel transistor connected between the gate of the N-channel transistor 44 and the output terminal of the second inverter circuit 16. The gates of the P-channel transistor 38 and N-channel transistor 42 are supplied with an output of the delay circuit 27. The gates of the P-channel transistor 34 and N-channel transistor 36 are supplied with an output of the second-stage inverter 30. The output of the inverter 30 is an inverted signal of an output of the delay circuit 27.
The operation principle of the above output circuit is described in detail in Japanese Patent Disclosure No. 63-132523, but is explained briefly hereinafter.
FIG. 2 is an operation waveform diagram for illustrating the operation of the output circuit of FIG. 1. An input signal IN is supplied from the internal circuit of either a different integrated circuit or the same integrated circuit. Assuming now that the input signal IN is changed from the low level "L" to the high level "H" (FIG. 2A), for example, then the output of the first inverter circuit 14, i.e., potential of a node 60 is inverted from "H" to "L" (FIG. 2B). As a result, the output of the second inverter circuit 16, i.e., potential of a node 61 is inverted from "L" to "H" (FIG. 2C) and the output of the third inverter circuit 18 is inverted from "H" to "L". Therefore, the output of the output buffer circuit 20, i.e., potential of the output terminal 22 is inverted from "H" to "L", and thus the inverted level "L" of the input signal IN can be derived at the output terminal (FIG. 2D). When the output signal OUT is changed from " H" to "L", charges on the capacitor 24 abruptly flow into the V.sub.ss potential line, to thereby cause the power source fluctuation. In this case, if a plurality of output signals corresponding to plural-bit data are simultaneously changed, then the power source fluctuation is enhanced.
Further, the output of the second-stage inverter 30 of the delay circuit 27, i.e., potential of a node 62 is changed from "H" to "L" (FIG. 2E) when the delay time of the delay circuit 27 has elapsed after the output signal OUT has changed from "H" to "L". The output of the third-stage inverter 32, i.e., potential of a node 63 is then changed from "L" to "H" (FIG. 2F). In a time period during when the output of the second-stage inverter 30 and the output of the third-stage inverter 32 are set at "H" and "L", respectively, the P-channel transistor 34 and the N-channel transistor 36 are kept in the OFF and ON states respectively according to the output "H" of the second-stage inverter 30, and also the P-channel transistor 38 and the N-channel transistor 42 are kept in the ON and OFF states respectively according to the output "L" of the third-stage inverter 32. As a result, when the output of the second inverter circuit 16 is in the "L" state before inversion, the P-channel transistor 40 is kept in the OFF state since the V.sub.cc potential is applied to the gate thereof via the P-channel transistor 38, and also the N-channel transistor 44 is kept in the OFF state since an output "L" of the second inverter circuit 16 is applied to the gate thereof via the N-channel transistor 36. In contrast, when the output of the second inverter circuit 16 is inverted completely to "H" during the delay operation of the delay circuit 27, the N-channel transistor 44 is set into the ON state since an output "H" of the second inverter circuit 16, i.e., potential of a node 65 is applied to the gate thereof via the N-channel transistor 36. The output "L" of the first inverter circuit 14 which has already been inverted is latched (FIG. 2H).
Further, when the output of the second-stage inverter 30 is inverted from "H" to "L" and the output of the third-stage inverter 32 is inverted from "L" to "H" at the time of completion of the delay operation of the delay circuit 27, then the P-channel transistor 34 and N-channel transistor 36 are inverted into the ON and OFF states respectively according to the output "L" of the second-stage inverter 30, and also the P-channel transistor 38 and N-channel transistor 42 are inverted into the OFF and ON states respectively according to the output "H" of the third-stage inverter 32. Therefore, the P-channel transistor 40 is kept in the OFF state since an output "H" of the second inverter circuit 16 is applied to the gate thereof via the P-channel transistor 34. The N-channel transistor 44 is returned to the OFF state since the V.sub.ss potential is applied to the gate thereof via the N-channel transistor 42.
Assuming then that the input signal IN is changed from "H" to "L", an operation similar to the above operation is effected. The main points of the operations are explained hereinbelow. When the output of the second inverter circuit 16 is inverted to be "L" level during the delay operation of the delay circuit 27, then the P-channel transistor 40 is inverted into the ON state since an output "L" of the second inverter circuit 16, i.e., potential of a node 64 is applied to the gate thereof via the P-channel transistor 34. An output "H" of the first inverter circuit 14, i.e., potential of the node 60 which has already been inverted is latched (FIG. 2G). Then, after completion of the delay operation, the P-channel transistor 40 is returned to the OFF state since the V.sub.cc potential is applied to the gate thereof via the P-channel transistor 38.
FIG. 3 is a circuit diagram showing another arrangement of the conventional output circuit. The output circuit shown in FIG. 3 is similar to the output circuit of FIG. 1 except that the third inverter circuit 18 is omitted, a delay circuit 27' is constructed by four series-connected inverters 50, 28, 30 and 32, and the gates of the P-channel transistor 34 and the N-channel transistor 36 are applied with an output of the third-stage inverter 30. The output of the inverter 30 has an inverted phase of the output of the delay circuit 27'. The same portions of FIG. 3 as those of FIG. 1 are denoted by the same reference numerals and the explanation thereof is therefore omitted.
However, in the conventional output circuits in FIGS. 1 and 3, single-channel type MOS transistors, i.e., P-channel transistor 34 and N-channel transistor 36 are used as transfer gates. The transfer gates transfer to the gates of the transistors 40 and 44 the potentials which selectively turn on the P-channel transistor 40 and N-channel transistor 44 to temporarily latch the input signal IN until the power source fluctuation caused by the change of the outputsignal OUT is suppressed. As a result, if the operation voltage of the power source is lowered, i.e., power source potential V.sub.cc is lowered, then the ON-resistances of the transfer gates are increased due to the back-gate bias effect and thus the propagation delays thereof are also increased. This makes it impossible to effect the latching operation at a desired timing as described above. In the worst case, the transfer gates are turned off and desired potentials cannot be transferred to the gates of the MOS transistors 40 and 44.
More particularly, the N-channel transistor 36 transfers not only a low level signal, but also a high level signal, and the P-channel transistor 34 transfers not only a high level signal but also a low level signal. In a case where a high level signal is transferred by means of the N-channel transistor 36, only a signal of a level V.sub.cc -V.sub.thN which is lowered by the threshold voltage V.sub.thN can be transferred. Therefore, as shown in FIG. 2H, the level of a signal "H" cannot be set sufficiently high. When the back-gate bias effect is taken into consideration, the threshold voltage V.sub.thN is increased and the level of the transferred signal is further decreased. On the other hand, in a case where a low level signal is transferred by means of the P-channel transistor 34, only a signal of a level V.sub.ss +.vertline.V.sub.thp .vertline. which is largely deviated from the level of a desired signal can be transferred. Therefore, as shown in FIG. 2G, the level of a signal "L" cannot be set sufficiently low. Since the signals of the transfer level set by the N-channel transistor 36 and the P-channel transistor 34 are input to gates of the N-channel transistor 44 and the P-channel transistor 40, it becomes difficult for the N-channel transistor 44 and the P-channel transistor 40 to be turned on when the operation voltage of the power source, i.e., power source potential V.sub.cc is lowered. Finally the transistors 44 and 40 cannot be turned on. Namely, the power source voltage dependency, by which the minimum operation voltage is limited, occurs.
Thus, the conventional output circuit uses single-channel type MOS transistors as transfer gates for transferring the potentials which turn on selectively the P-channel transistor 40 and the N-channel transistor 44 to temporarily latch the input signal until the power source fluctuation caused by the change of the output signal is suppressed. Therefore, when the operation voltage of the power source is lowered, i.e., power source potential V.sub.cc is lowered, the ON-resistances of the transfer gates are increased owing to the back-gate bias effect and the propagation delays of the transfer gates become large. This makes it impossible to effect the latching operation at a desired timing as described above. In the worst case, the transfer gates are turned off, making it impossible to transfer desired potentials.